Weighted sum codes for error detection

ABSTRACT

A new class of error detection codes has powerful error detection properties, as well as significant implementation advantages. The inventive error detection codes are used in communication protocols to protect transmitted data from corruption.

FIELD OF THE INVENTION

The present invention relates to an error detection code used to protect data transmitted via a high speed communication channel from corruption.

BACKGROUND OF THE INVENTION

A network communication protocol uses error detection codes to protect data from corruption. The transmitter calculates parity bits and appends the parity bits to a block of data which is transmitted to a receiver. The receiver recalculates the parity bits based on the information it receives. Only if the received and receiver calculated parities are identical is the received block of data assumed to be error free. The code used to calculate the parities determines how well the information is protected and how easy it is to calculate the parities.

FIG. 1 shows a typical communication system 10. The transmitter 12 appends an h-bit parity word P to a k-bit data word Q to form a redundant codeword R. The parity word P is calculated using a particular error correction code. The redundant codeword R is transmitted via channel 14 to a receiver 16. The redundant codeword R may be corrupted in the channel 14 due to noise or other reasons. Thus, the codeword that is received at the receiver 16 is designated R*.

The received codeword R* may be viewed as being formed by the polynomial addition of R and an error polynomial E. The error polynomial E has non-zero terms in those bit positions where there is an error. Because R is a valid codeword and polynomial addition is linear, R* will be a valid codeword only if the error polynomial E is also a valid codeword. Thus, an error will be detected at the receiver as long as the error polynomial E is not also a valid codeword. FIG. 2 shows the binary representation of Q, P, R and E.

For some error detection codes, the k-bit data word Q is divided into a plurality of h/2-bit symbols, each of which is labeled Q_(i). Similarly, the transmitted redundant codeword R may be divided into h/2-bit symbols labeled R_(i). In this case, the parity word P is divided into two h/2-bit symbols, the top half parity symbol P₁ and the bottom half parity symbol P₀. FIG. 3 shows the binary representations of P₀, P₁ and Q_(i).

There are four error detection parameters which may be utilized in characterizing the error detection capabilities of an error detection code. These parameters are:

h--numbers of redundant (i.e. parity) bits

k--maximum number of message bits that can be protected using h parity bits

d--minimum number of bits that must be changed to make any codeword of (h+k) bits into any other codeword

b--maximum error burst length that is always detected, e.g. if an error changes bits 11, 13 and 15, the burst length is five.

The number of parity bits h is the key parameter for an error detection code because the chance of a random error resulting in the correct parities is at least 2^(-h). An error detection code with distance d guarantees detecting all errors which change less than d bits in a block of k bits.

Typically, the number of parity bits h is fixed by the application requirements. Once h is fixed, the three remaining parameters used to describe the error detection capabilities should be as follows:

d large as possible to detect all small errors

b large as possible to detect a large single block of errors

k large as possible to allow large error detection blocks

There are a number of error detection codes disclosed in the prior art. However, the prior art error correction codes have certain shortcomings. For example, the well known CRC (Cyclic Redundancy Code) has very strong error detection characteristics. However, the CRC requires data to be processed in the originally transmitted order. In addition, some embodiments of the CRC code are very slow when implemented in software. The CRC code is disclosed in W. W. Peterson et al., "Cyclic Codes for Error Detection," Proceedings of the IRE, pp. 228-235, January 1961. Another prior art error detection code is the Fletcher Checksum. The Fletcher Checksum can be implemented efficiently in software but has weaker error detection capabilities than CRC and still requires perfectly ordered data. The Fletcher Checksum is disclosed in J. G. Fletcher, "An Arithmetic Checksum For Serial Transmissions," IEEE Transactions on Communications, Vol. COM-80, No. 1, pp. 247-252, January 1982. The TCP (Transmission Control Protocol) offers efficient software implementation and out of order processing, but it has even weaker error detection properties. The TCP is disclosed in Department of Defense, "Transmission Control Protocol," MIL-STD-1778, May 1983. Another error detection code known as XTP CXOR is disclosed in XTP Definition 3.5, 1991m "Appendix A: Check Function," Protocol Engines Inc., 1421 State Street, Santa Barbara, Calif. 93101.

It is an object of the present invention to provide an error detection code which overcomes the shortcomings of the prior art error correction codes. More specifically, it is an object of the invention to provide an error detection code which has powerful error detection properties (i.e., large d, b, k for a given h) but also has a simple software and/or hardware implementation.

SUMMARY OF THE INVENTION

In a preferred embodiment, the present invention is directed to a method for coding data to be transmitted using a unique error detection code. The error detection code of the present invention is referred to as a Weighted Sum Code. The Weighted Sum Code of the present invention utilizes polynomial arithmetic for its calculations. The Weighted Sum Code divides each k-bit data word Q into one or more symbols Q_(i) each of which has h/2 bits. The parity word P is divided into a bottom half parity symbol P₀ and a top half parity symbol P₁, each of which has h/2 bits. In accordance with the invention, the parity symbols P₀ and P₁ are chosen as follows: ##EQU1## These equations can be rewritten as

    P.sub.1 =W.sub.(2k/h)-1 ×Q.sub.(2k/h)-1 ⊕W.sub.2k/h)-2 ×Q.sub.(2k/h)-2 ⊕. . . ⊕W.sub.0 ×Q.sub.0 mod M (1)

    P.sub.0 =Q.sub.(2k/h)-1 ⊕Q.sub.(2k/h)-2 ⊕.. . ⊕Q.sub.0 ⊕P.sub.1                                              ( 2)

In equations (1) and (2), multiplication (×) and addition (⊕) are of two h/2 bit polynomials. For example, if h=8, then a minimum sized codeword (with k=4) comprises a four bit message (Q_(o)) and two four-bit parity symbols (P₀ and P₁).

When the data and parity symbols are expanded into their binary polynomial representations, equation (1) becomes: ##EQU2## and equation (2) becomes: ##EQU3##

In equations (1) and (3), the modulus M is a primitive polynomial of degree h/2 (e.g. h=8, M=x⁴ +x+1; h=16, M=x⁸ +x⁴ x³ +x² +1). The h/2-bit weight symbols W are chosen so that they go through a maximal length sequence including all possible 2.sup.(h/2) symbols except for zero and one.

The inventive Weighted Sum Codes are used in accordance with the present invention as follows. At a transmitter, a k-bit message Q comprised of h/2-bit symbols Q_(i) is generated. A processor, in the form of a general purpose microprocessor or other CPU or a special purpose circuit, calculates the parity symbols P₀ and P₁. The parity symbols P₀, P₁ are appended to the message Q to form the redundant codeword R. The redundant codeword R is transmitted via a communication channel to a receiver. The receiver, using a general purpose microprocessor or other CPU or a special purpose hardware circuit, recalculates the parity symbols P₀, P₁ to determine if any bits were transmitted in error.

The Weighted Sum Codes of the present invention have some extremely desirable error detection characteristics. The Weighted Sum Codes have the same distance (d) and burst error protection (b) as CRC. The inventive Weighted Sum Codes have a smaller but still acceptable maximum error detection block size. Specifically in CRC:

d=4

b=h

k=2^(h)

In the Weighted Sum Codes of the present invention:

d=4

b=h

k=(h/2)×(2^(h/2) -1)

Moreover, the inventive Weighted Sum Codes are easy to implement in both software and hardware and have the ability to process data in any order.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 schematically illustrates a communication system.

FIG. 2 and FIG. 3 are tables which provide binary representations for various quantities used in the transmission of messages that are coded for error protection.

FIG. 4 illustrates a program for calculating a bottom half parity symbol P₀ in accordance with the invention.

FIG. 5 illustrates a program for calculating a top half parity symbol P₁ for one Weighted Sum Code in accordance with the invention.

FIG. 6 illustrates a program for calculating a top half parity symbol P₁ for a second Weighted Sum Code in accordance with the invention.

FIG. 7 illustrates a circuit for determining parity symbols P₁ and P₀ for a first weighted sum code in accordance with the invention.

FIG. 8 illustrates a circuit for determining parity symbols P₁ and P₀ for a second Weighted Sum Code in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

Two examples of the Weighted Sum Codes of the present invention known as WSC-1 and WSC-2, are provided below,

A) WSC-1

The WSC-1 error detection code uses weights defined by

    W.sub.i =x.sup.(i+l) mod M

    W.sub.0 =x,W.sub.1 x.sup.2, W.sub.2 =x.sup.3, W.sup.3 =x.sup.4 . . . (5)

Therefore from equations (1) and (5)

    P.sub.1 =(x.sup.(2k/h))×Q.sub.(2k/h)-1 ⊕(x.sup.2k/h)-1)×Q.sub.(2k/h)-2 ⊕. . . ⊕(x)×Q.sub.0 mod M                              (6)

P₀ is then determined according to equation (2).

WSC-1 uses equations (6) and (2) to generate the parity symbols P₁ and P₀ from the data symbols Q_(i). For example, with h=8 and M=x⁴ +x+1, if it is desired to transmit the k=16 bits of data Q=1101 0111 0101 1010, then from equation (6), it can be determined

    P.sub.1 =(x.sup.4)×(x.sup.3 +x.sup.2 +1)+(x.sup.3)×(x.sup.2 +x+1)+(x.sup.2 )×(x.sup.2 +1)+(x)×(x.sup.3 +x)mod x.sup.4 +x+1

    P.sub.1 =x.sup.7 +x.sup.6 +x.sup.5 +x.sup.3 mod x.sup.4 +x+1

    P.sub.1 =x.sup.3 +1=1001                                   (7)

and

    P.sub.0 =(x.sup.3 +x.sup.2 +1)+(x.sup.2 +x+1)+(x.sup.2 +1)+(x.sup.3 +x)+P.sub.1

    P.sub.0 =(x.sup.3 +x.sup.2 +1)+(x.sup.2 +x+1)+(x.sup.2 +1)+(x.sup.3 +x)+(x.sup.3 +1)

    P.sub.0 =x.sup.3 +x.sup.2 =1100                            (8)

Therefore, the transmitted redundant codeword is by R=Q,P₁,P₀ =1101 0111 0101 1001 1100

B) WSC-2

The WSC-2 error detection code uses weights defined by

    W.sub.i =[i+2]mod M                                        (9)

where [i+2] means the polynomial representation of the integer [i+2], i.e. ##EQU4##

Using equation (9) and equation (1), the parity symbol P₁ is given by

    P.sub.1 =([(2k/h)+1])×Q.sub.(2k/h)-1 ⊕([2k/h)])×Q.sub.(2k/h)-2 ⊕. . . ⊕(x)×Q.sub.0 mod M                                                         (10)

The parity symbol P₀ is then given by equation (2).

For example, with h=8 and M=x^(4+x+) 1, to transmit Q=1101 0101 1010, it can be determined that

    P.sub.1 =(x.sup.2 +1)×(x.sup.3 +x.sup.2 +1)+(x.sup.2)×(x.sup.2 +x+1) +(x+1)×(x.sup.2 +1)+(x)×(x.sup.3 +x)mod x.sup.4 +x+1

    P.sub.1 =x.sup.5 +x.sup.4 +x.sup.3 +x.sup.2 +x mod x.sup.4 +x+1

    P.sub.1 =x.sup.3 +x+1=1011                                 (11)

and

    P.sub.0 =(x.sup.3 +x.sup.2 +1)+(x.sup.2 +x+1)+(x.sup.2 +1)+(x.sup.3 +x)+P.sub.1

    P.sub.0 =(x.sup.3 +x.sup.2 +1)+(x.sup.2 +x+1)+(x.sup.2 +1)+(x.sup.3 +x )+(x.sup.3 +x)+(x.sup.3 +x+1)

    P.sub.0 =x.sup.3 +x.sup.2 +x=1110                          (12)

The transmitted redundant codeword R=Q,P₁, P₀ is given by R=1101 0111 0101 1010 1011 1110

C) Software Implementation

The Weighted Sum Codes of the present invention may in particular cases be implemented in software or hardware. An illustrative software implementation is considered first.

A program in pseudocode for calculating P₀ by implementing equation 2 is shown in FIG. 4.

In each clock cycle, the program of FIG. 4 takes a symbol of data Q_(i) in any order and adds it using bitwise exclusive-OR addition to the current partial parity symbol P₀. Finally, the program of FIG. 4 adds P₁ to the last partial parity symbol P₀ to obtain a final value for P₀. The program of FIG. 4 is useful for all embodiments of the Weighted Sum Codes.

FIG. 5 illustrates a program for determining P₁ for the WSC-1 code. The program of FIG. 5 does not directly implement equation (6). Instead, equation (6) is rewritten recursively as follows

    ((. . . ((((Q.sub.(2k/h)-1) ×x)⊕Q.sub.2k/h-2) ×x)⊕. . . ⊕Q .sub.0)×x)⊕P.sub.1 =0 mod M (            (13)

The program of FIG. 5 implements equation (13). The program starts with the most significant symbol of data Q.sub.(2k/h-1) and works down. In the worst case, the main loop (lines 4-7) has two adds, a multiply by two, a logical AND, and a test. The program of FIG. 5 is illustrated below using the above-described example where h=8, M=x⁴ +x+1 and Q=1101 0111 0101 1010.

initially:

    P.sub.1 =0

i=3:

    P.sub.1 =(((0)+(x.sup.3 +x.sup.2 +1))×x mod x.sup.4 +x+1=(x .sup.4 +x.sup.3 +x)+(x.sup.4 +x+1)=x.sup.3 +1

i=2:

    P.sub.1 =((x.sup.3 +1)+(x.sup.2 +x+1))×x mod x.sup.4 +x+1=(x.sup.4 + x.sup.3 +x.sup.2)+(x.sup.4 +x+1)=x.sup.3 +x.sup.2 +x+1

i=1:

    P.sub.1 =((x.sup.3 +x.sup.2 +x+1)+(x.sup.3 +x))×x mod x.sup.4 +x+1 =(x.sup.4 +x.sup.3 x+)+(x.sup.4 +x+1)=x.sup.3 +x+1

i=0:

    P.sub.1 =((x.sup.2 +x+1)+(x.sup.3 +x))×x mod x.sup.4 +x+1=(x.sup.4 +x.sup.3 +x)+(x.sup.4 +x+1)=x.sup.3 +`

FIG. 6 illustrates a program for determining P₁ for the WSC-2 code. In each clock cycle, the program of FIG. 6 takes a symbol of data Q_(i), in any order, multiplies it with the symbol's index i, then adds it using bitwise exclusive-OR addition with the current partial parity P₁. The subroutine for poly-multiply (line 5 of FIG. 6) operates in a serial mode with a main loop of h/2 cycles. Thus, the number of instructions is proportional to h.

Preferably, when a software implementation of the inventive Weighted Sum Codes is used, the programs for determining P₁ and P₀ are executed by a general purpose processor (e.g. a microprocessor) located in a transmitter. The resulting values of P₁ and P₀ are then appended to a data word Q to form a redundant code word R. The redundant code word R is then transmitted via a communications channel to a receiver. The receiver also includes a microprocessor which executes the program to recalculate P₁ and P₀. The transmitted and recalculated values of P₁ and P₀ are compared to determine if there are any transmission errors.

D) Hardware Implementation

Instead of using a microprocessor at the transmitter and receiver to determine P₁ and P₀, special purpose circuitry may be used.

FIG. 7 illustrates a circuit 10 for determining P₁ and P₀ for WSC-1.

The circuit 10 comprises a first circuit 12 for determining P₀ according to equation (2) and a second circuit 14 determining P₁ according to equation (13).

The circuit 10 also includes a multiplexer 20. The multiplexer has three inputs labeled P₁, P₀, and Q_(i). The multiplexer selectively passes one of these inputs to the single multiplexer output.

The circuit 14 for determining P₁ comprises two h/2-bit polynomial adders 32 and 34, an h/2-bit multiplexer 36 and an h/2-bit register 38. The circuit 14 implements the loop set forth in lines 3-8 of FIG. 5. Initially, P1 is set equal to zero. During each cycle, a symbol Q_(i) is inputted from the multiplexer 20 to the circuit 14. The h/2-bit adder implements the addition step of line 5 of FIG. 5 as well as the multiply by 2 (i.e. left shift) step of line 6. The step in line 7 wherein P₁ →P₁ ⊕M is implemented by the h/2-bit adder 34. The "if" statement of line 7 is implemented by the multiplexer 36. The resulting partial parity symbol P₁ obtained after each cycle is stored in the register 38. The partial parity symbol P₁ stored in the register 38 is then fed back to the adder 32. The process is continued until the final value of P₁ is stored in the register 38.

The circuit 12 for determining P₀ comprises an h/2-bit adder 40 and an h/2-bit register 42. The value of P₀ is initially set to zero and stored in the register 42. During each cycle (except the last cycle) the multiplexer 20 output a symbol Q_(i) to the adder 40 and the partial P₀ value stored in the register 42 is also outputted back to the adder 40. The adder 40 adds the partial P₀ value and Q_(i) and stores the new partial P₀ value in the register 42. In the last cycle, the multiplexer outputs P₁ to the adder 40. The adder 40 adds P₁ and the partial P₀ value in the register 42 to obtain the final value for P₀.

FIG. 8 illustrates a circuit for determining P₁ and P₀ for the WSC-2 code mentioned above.

The circuit 50 of FIG. 8 comprises a circuit 12 for calculating P₀ and a multiplexer 20. The circuit 12 and multiplexer 20 are identical to the corresponding elements of FIG. 7. The circuit 50 of FIG. 8 also comprises a circuit 60 for determining P₁. The circuit 60 comprises an h/2-bit multiplexer 62, an h/2-bit adder 64 and an h/2-bit register 66. The circuit 60 operates by implementing the steps of lines 2-5 of the program of FIG. 6. Initially, a partial value of P₁ is set to zero and stored in the register 66. In each cycle, the multiplier 62 receives a data symbol Q_(i) from the multiplexer 20 and a sequence number 10 from the input 61. The multiplier 62 multiplies Q_(i) by the polynomial [i]. The result is added by the adder 64 to the partial P₁ value stored in the register 66 to form a new-partial P₁ value which is stored in the register 66. The process continues until the final value of P₁ is stored in the register 66.

In short, a new set of error detection codes has been disclosed. The error detection codes are used to detect errors in data transmitted over a communication channel. The new error detection codes have strong error detection capabilities as well as significant implementation advantages. Finally, the above described embodiments of the invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the spirit and scope of the following claims. 

I claim:
 1. A method for transmitting a k bit data word Q via a communication channel, wherein said data word Q comprises one or more h/2 bit data symbols Q_(i), were h and k are positive integers, said method comprising the steps of:at a transmitter, determining a first parity symbol P₁ where P₁ is given by

    P.sub.1 =W.sub.(2k/h)-1 ×Q.sub.(2k/h)-1 ⊕W.sub.(2k/h)-2 ×Q.sub.(2k/h)-2 ⊕. . . ⊕W.sub.0 ×Q.sub.0 mod M;

at said transmitter, determining a second parity symbol P₀, where P₀ is given by

    P.sub.0 =Q.sub.(2k/h)-1 ⊕Q.sub.(2k/h)-2 ⊕. . . ⊕Q.sub.0 ⊕P.sub.1 ;

forming a redundant codeword R which includes said data word Q and said first and second parity symbols P₁ and P₀ ; and transmitting said redundant codeword R from said transmitter via said communication channel to a receiver, wherein said first and second parity symbols P₁ and P₀ have h/2 bits, each W is a weight symbol, and M is a primitive polynomial of degree h/2.
 2. The method of claim 1 further comprising the steps of:receiving said redundant codeword R at said receiver after transmission via said channel, recalculating said first and second parity symbols P₀ and P₁ at said receiver, and comparing the recalculated first and second parity symbols P₀ and P₁ with the first and second parity symbols P₀ and P₁ transmitted from said transmitter.
 3. The method of claim 1 wherein said weight symbols W are given by

    W=x.sup.(i+1) mod M

where x is a variable used in the representative of polynomials.
 4. The method of claim 1 wherein said weight symbols W are given by

    W.sub.i =[i+2]mod M

where [[j]] [i+2] indicates the polynomial representation of the integer [j]i+2.
 5. A method for redundantly encoding a k bit data word Q comprised of one or more h/2 bit symbols Q_(i) to enable subsequent detection of an error in the data word Q, where h and k are positive integers, said method comprising the steps of:(1) at an encoding device, electronically determining a first parity symbol P₁, where P₁ is given by

    P.sub.1 =W.sub.2k/h)-1 ×Q.sub.(2k/h)-1 ⊕W.sub.2k/h)-2)×Q.sub.(2K/h)-2 ⊕. . . ⊕W.sub.0 ×Q.sub.0 mod M;

(2) at said encoding device, electronically determining a second parity symbol P₀, where P₀ is given by

    P.sub.0 =1.sub.(2k/h)-1 ⊕Q.sub.(2k/h)-2 ⊕. . . ⊕Q.sub.0 ⊕P.sub.1 ; and

(3) encoding said data word Q to enable the subsequent detection of an error in said data word Q by forming a redundant codeword including said data word Q and said first and second parity symbols P₁ and P₀, wherein said first and second parity symbols P₁ and P₀ have h/2 bits, each W is a weight symbol, and M is a primitive polynomial of degree h/2.
 6. The method of claim 5 further comprising the step of transmitting said redundant codeword via a communication channel to a receiver.
 7. The method of claim 6 further comprising the step of recalculating said first and second parity symbols P₁ and P₀ at said receiver to determine if said redundant codeword received at said receiver contains an error introduced by said communication channel.
 8. The method of claim 5 wherein each weight set W consisting of the h/2 bits symbols Wi contains all possible 2.sup.(h/2) values except zero and one. 